1. Field of the Invention
In general, the present invention relates to a continuous-time-system ΔΣ modulator applied to audio-electronic and medical-treatment/measurement apparatus and the like in addition to radio-communication receivers which serve as main applications. More particularly, the present invention relates to a loop delay compensation circuit of the ΔΣ modulator.
2. Description or the Related Art
FIG. 1 is a block diagram showing an ordinary second-order low-pass ΔΣ modulator 1 of the continuous time system.
The ΔΣ modulator 1 shown in the block diagram of FIG. 1 is configured to employ integrators INT1 and INT2, a quantizer Quan, adders ADD1 and ADD2 as well as DA (Digital-to-Analog) converters DAC1 and DAC2.
In the block diagram of FIG. 1, reference notation u denotes an analog input signal whereas reference notation v denotes a digital output signal. Reference notations a1 and a2 denote the feedback gains of the DA converters DAC1 and DAC2 respectively whereas reference notations c1 and c2 denote the gains of the integrators INT1 and INT2 respectively. Reference notation Q denotes the effective gain of the quantizer Quan.
For the ΔΣ modulator 1 shown in the block diagram of FIG. 1, the NTF (noise transfer function) of quantization noises to the digital output signal v is expressed by an equation given below. The quantization noises are quantization error generated in the quantizer Quan. The NTF expressed by the equation shows a high-pass frequency characteristic.
                    NTF        =                              s            2                                              s              2                        +                                          a                1                            ⁢                              c                1                            ⁢              Qs                        +                                          a                2                            ⁢                              c                1                            ⁢                              c                2                            ⁢              Q                                                          (        1        )            
That is to say, the quantization noises generated by the quantizer Quan in the ΔΣ modulator 1 are subjected to a noise shaping process due to a feedback effect in order to shift the noises to a high-frequency region. Thus, in the signal band of the low-frequency region, a high SNR (signal to noise ratio) is obtained.
If processing delays are introduced by the quantizer Quan and/or the DA converters DAC1 and DAC2 in the ΔΣ modulator 1 shown in the block diagram of FIG. 1, however, the NTF expressed by the above equation no longer holds true in a strict manner. In this case, the effect of the noise shaping process may become smaller so that the SNR deteriorates. In addition, in some cases, the feedback loop of the ΔΣ modulator 1 may oscillate.
In order to solve the problems raised by the DE modulator 1 as described above, loop-delay compensation technologies have been developed. Typical loop-delay compensation technologies are described in JP-T-2002-528989 and JP-T-2003-534679 (hereinafter referred to as Patent Documents 1 and 2, respectively) as well as “A Low-Noise Low-Voltage CT ΔΣ Modulator with Digital Compensation of Excess Loop Delay,” IEEE, International Solid-State Circuits Conference, 2005, pp. 498 to 499 and “A 1.8-mW CMOS ΔΣ Modulator with Integrated Mixer for A/D Conversion of IF Signals,” IEEE, Journal of Solid-State Circuits, Vol. 35, No. 4, April 2000 (hereinafter referred to as Non-Patent Documents 1 and 2, respectively).
FIG. 2 is a block diagram showing a ΔΣ modulator 2 which has a delay compensation function disclosed in Patent Document 1.
The ΔΣ modulator 2 shown in the block diagram of FIG. 2 employs an S/H (Sample/Hold) circuit SH1 and a compensation filter FLT1 which are provided at the input stage in front of the quantizer Quan. The compensation filter FLT1 feeds an output signal of the S/H circuit SH1 back to the S/H circuit SH1 so as to compensate the input-to-output voltage transfer function for effects of the problems raised by the ΔΣ modulator 1.
FIG. 3 is a block diagram showing the (compensation) filter circuit FLT1 employed in the ΔΣ modulator 2 shown in the block diagram of FIG. 2.
By properly setting the input-to-output voltage transfer function of the compensation filter FLT1, it is possible to compensate the input-to-output voltage transfer function of the ΔΣ modulator 2 for effects of the problems raised by the ΔΣ modulator 1.
FIG. 4 is a block diagram showing a ΔΣ modulator 3 which has a delay compensation function disclosed in Patent Document 2.
The configuration of the ΔΣ modulator 3 shown in the block diagram of FIG. 4 employs another DA converter DAC3 which feeds an output signal of the quantizer Quan back to the input node of the quantizer Quan so as to compensate the input-to-output voltage transfer function of the ΔΣ modulator 3 for the problems raised by the ΔΣ modulator 1. This delay compensation technique is the contemporary technique most widely adopted to compensate the input-to-output voltage transfer function of a ΔΣ modulator for effects of the delay problems described above.
FIG. 5 is a block diagram showing a ΔΣ modulator 4 which has a delay compensation function described in non-Patent Document 1.
The ΔΣ modulator 4 shown in the block diagram of FIG. 5 is configured to serve as a modulator which is capable of carrying out the delay compensation process as digital signal processing. In comparison with the ΔΣ modulator 3 shown in the block diagram of FIG. 4, the ΔΣ modulator 4 employs a register and an adder in place of the other DA converter DAC3 provided for the delay compensation purpose.
FIG. 6 is a block diagram showing a ΔΣ modulator 5A which has a delay compensation function disclosed in non-Patent Document 2.
The ΔΣ modulator 5A shown in the block diagram of FIG. 6 is configured to function as a modulator which is capable of adjusting coefficients in order to compensate the input-to-output voltage transfer function of the ΔΣ modulator 5A for function changes caused by delays. In order to compensate the input-to-output voltage transfer function of the ΔΣ modulator 5A, the ΔΣ modulator 5A employs a path which is added to the integrator INT1 as a path including only constant-term elements.
FIG. 7 is a circuit diagram showing the integrator INT1 provided with a path which includes only constant-term elements.
In the configuration of the integrator INT1 provided with a path including only constant-term elements, in order to implement the constant term, a resistor Rint is connected in series to the capacitor Cint. Since the resistor Rint is the only element required for the delay compensation, both the power consumption and the circuit size are smallest among the circuits of the proposed ΔΣ modulators described above.